71. G. S. Lin and J. B. Kuo, “Fringing-Triggered Narrow-Channel-Impression (FINCE) Relevant Capacitance Conclusion off Nanometer FD SOI NMOS Gadgets Having fun with Mesa-Separation Thru three dimensional Simulation” , EDSM , Taiwan ,

72. J. B. Kuo, “Development of Bootstrap Techniques in Lower-Voltage CMOS Digital VLSI Circuits getting SOC Apps” , IWSOC , Banff, Canada ,

P. Yang, “Entrance Misalignment Impression Related Capacitance Choices off an effective 100nm DG FD SOI NMOS Tool which have letter+/p+ Poly Finest/Base Door” , ICSICT , Beijing, China

73. Grams. Y. Liu, N. C. Wang and J. B. Kuo, “Energy-Productive CMOS High-Weight Rider Routine to your Complementary Adiabatic/Bootstrap (CAB) Technique for Reduced-Stamina TFT-Lcd Program Programs” , ISCAS , Kobe, The japanese ,

74. Y. S. Lin, C. H. Lin, J. B. Kuo and you will K you could try here. W. Su, “CGS Capacitance Trend out of 100nm FD SOI CMOS Gadgets that have HfO2 High-k Gate Dielectric Considering Straight and you can Fringing Displacement Outcomes” , HKEDSSC , Hong kong ,

75. J. B. KUo, C. H. Hsu and you may C. P. Yang, “Gate-Misalignment Relevant Capacitance Choices out of a good 100nm DG SOI MOS Equipment having N+/p+ Top/Bottom Gate” , HKEDSSC , Hong-kong ,

76. Grams. Y. Liu, Letter. C. Wang and you can J. B. Kuo, “Energy-Successful CMOS Highest-Stream Driver Routine toward Subservient Adiabatic/Bootstrap (CAB) Way of Reduced-Energy TFT-Liquid crystal display Program Apps” , ISCAS , Kobe, The japanese ,

77. H. P. Chen and J. B. Kuo, “A good 0.8V CMOS TSPC Adiabatic DCVS Logic Circuit towards Bootstrap Technique for Lowest-Stamina VLSI” , ICECS , Israel ,

B. Kuo, “A book 0

80. J. B. Kuo and you may H. P. Chen, “A reduced-Voltage CMOS Load Rider toward Adiabatic and you will Bootstrap Tricks for Low-Electricity Program Software” , MWSCAS , Hiroshima, The japanese ,

83. Meters. T. Lin, E. C. Sun, and you can J. B. Kuo, “Asymmetric Gate Misalignment Impact on Subthreshold Features DG SOI NMOS Devices Offered Fringing Electronic Field-effect” , Electron Gizmos and you may Thing Symposium ,

84. J. B. Kuo, E. C. Sunrays, and you will M. T. Lin, “Data regarding Gate Misalignment Influence on brand new Threshold Current out-of Twice-Door (DG) Ultrathin FD SOI NMOS Products Playing with a concise Model Offered Fringing Electric Field-effect” , IEEE Electron Gadgets getting Microwave and Optoelectronic Applications ,

86. Elizabeth. Shen and you will J. 8V BP-DTMOS Blogs Addressable Recollections Phone Routine Produced from SOI-DTMOS Process” , IEEE Fulfilling into the Electron Equipment and you may Solid state Circuits , Hong-kong ,

87. P. C. Chen and you can J. B. Kuo, “ic Logic Circuit Playing with an immediate Bootstrap (DB) Technique for Reduced-voltage CMOS VLSI” , Globally Symposium into the Circuits and you may Expertise ,

89. J. B. Kuo and S. C. Lin, “Lightweight Malfunction Design to have PD SOI NMOS Gadgets Considering BJT/MOS Effect Ionization to possess Liven Circuits Simulator” , IEDMS , Taipei ,

90. J. B. Kuo and S. C. Lin, “Lightweight LDD/FD SOI CMOS Equipment Model Given Opportunity Transportation and Mind Temperatures to own Liven Routine Simulation” , IEDMS , Taipei ,

91. S. C. Lin and you may J. B. Kuo, “Fringing-Caused Barrier Minimizing (FIBL) Aftereffects of 100nm FD SOI NMOS Devices with a high Permittivity Entrance Dielectrics and you can LDD/Sidewall Oxide Spacer” , IEEE SOI Fulfilling Proc , Williamsburg ,

ninety-five. J. B. Kuo and S. C. Lin, “The fresh Fringing Digital Field-effect into the Quick-Route Feeling Threshold Voltage out-of FD SOI NMOS Gadgets with LDD/Sidewall Oxide Spacer Build” , Hong kong Electron Gadgets Fulfilling ,

93. C. L. Yang and you may J. B. Kuo, “High-Temperature Quasi-Saturation Brand of Large-Voltage DMOS Electricity Gizmos” , Hong kong Electron Gadgets Fulfilling ,

94. Age. Shen and J. B. Kuo, “0.8V CMOS Blogs-Addressable-Recollections (CAM) Mobile Ciurcuit which have a fast Mark-Compare Possibilities Using Vast majority PMOS Dynamic-Tolerance (BP-DTMOS) Strategy Predicated on Basic CMOS Technology for Reasonable-Voltage VLSI Expertise” , Global Symposium on Circuits and Assistance (ISCAS) Procedures , Washington ,